Recently, to increase the packing density of semiconductor devices, there is demand for further thinning of line width. On the other hand, the resolution power of exposure apparatuses is approaching its limit. Thus, techniques for lithography in the resolution limit region are required. For lithography in the resolution limit region, the illumination condition of the exposure apparatus must be adapted to the finest pattern (closest pattern) in the semiconductor device. Thus, the problem is that it is difficult to ensure a sufficient lithography margin in the case of exposure for circuit patterns other than the closest pattern.
To improve the lithography margin, in a photomask, it is effective to provide a fine auxiliary pattern not resolved on the wafer, besides the main pattern corresponding to the circuit pattern to be formed. Conventionally, the placement position of the auxiliary pattern is determined by exhaustive or exploratory techniques. However, the placement position of the auxiliary pattern has a huge number of combinations. Hence, it takes a long time to determine the placement position of the auxiliary pattern.